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 SSM2602GY
N-CHANNEL ENHANCEMENT MODE POWER MOSFET
PRODUCT SUMMARY
Capable of 2.5V gate drive Lower on-resistance Surface mount package RoHS Compliant
S D D G D D
BVDSS RDS(ON) ID
20V 34m 6.3A
SOT-26
DESCRIPTION
Advanced Power MOSFETs utilized advanced processing techniques to achieve the lowest possible on-resistance, extremely efficient and cost-effectiveness device. The SOT-26 package is universally used for all commercial-industrial applications.
D
G S
Pb-free; RoHS-compliant
ABSOLUTE MAXIMUM RATINGS
Symbol VDS VGS ID@TA=25 ID@TA=70 IDM PD@TA=25 TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current , VGS @ 4.5V Continuous Drain Current , VGS @ 4.5V Pulsed Drain Current
1,2 3 3
Rating 20 12 6.3 5 30 2 0.016 -55 to 150 -55 to 150
Units V V A A A W W/
Total Power Dissipation Linear Derating Factor Storage Temperature Range Operating Junction Temperature Range
THERMAL DATA
Symbol Rthj-a Parameter Thermal Resistance Junction-ambient
3
Value Max. 62.5
Unit /W
11/16/2007 Rev.1.00
www.SiliconStandard.com
1
SSM2602GY
ELECTRICAL CHARACTERISTICS
(TJ=25 C unless otherwise specified)
Symbol BVDSS
BVDSS/Tj
o
Parameter Drain-Source Breakdown Voltage Static Drain-Source On-Resistance
2
Test Conditions VGS=0V, ID=250uA VGS=10V, ID=5.5A VGS=4.5V, ID=5.3A VGS=2.5V, ID=2.6A
Min. 20 0.5 -
Typ. 0.1 13 8.7 1.5 3.6 6 14 18.4 2.8 603 144 111
Max. Units 30 34 50 1 10 100 16 1085 V V/ m m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF
Breakdown Voltage Temperature Coefficient Reference to 25, ID=1mA
RDS(ON)
VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss
Gate Threshold Voltage Forward Transconductance
Drain-Source Leakage Current (Tj=25oC) Drain-Source Leakage Current (Tj=55oC)
VDS=VGS, ID=250uA VDS=5V, ID=5.3A VDS=20V, VGS=0V VDS=16V ,VGS=0V VGS= 12V ID=5.3A VDS=10V VGS=4.5V VDS=15V ID=1A RG=2,VGS=10V RD=15 VGS=0V VDS=15V f=1.0MHz
Gate-Source Leakage Total Gate Charge
2
Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance
2
SOURCE-DRAIN DIODE
Symbol VSD trr Qrr Parameter Forward On Voltage
2 2
Test Conditions IS=1.2A, VGS=0V IS=5A, VGS=0V, dI/dt=100A/s
Min. -
Typ. 16.8 11
Max. Units 1.2 V ns nC
Reverse Recovery Time
Reverse Recovery Charge
Notes:
1.Pulse width limited by Max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 3.Surface mounted on 1 in2 copper pad of FR4 board ; 156/W when mounted on min. copper pad.
11/16/2007 Rev.1.00
www.SiliconStandard.com
2
SSM2602GY
80
50
T A =25 o C
60
5.0V 4.5V 4.0V ID , Drain Current (A)
30
T A =150 C
40
o
5.0V 4.5V 4.0V
20
ID , Drain Current (A)
V G =2.5V
40
20
V G =2.5V
10
0 0 1 2 3 4 5 6 7
0 0 1 2 3 4 5 6 7 8
V DS , Drain-to-Source Voltage (V)
V DS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
100
1.8
I D = 1.0 A
o T A =25 C
80
I D =5.3A V G =4.5V Normalized RDS(ON)
1.4
RDS(ON) (m)
60
1.0
40
20 1 4 7 10
0.6 -50 0 50 100 150
V GS , Gate-to-Source Voltage (V)
T j , Junction Temperature ( o C)
Fig 3. On-Resistance v.s. Gate Voltage
Fig 4. Normalized On-Resistance v.s. Junction Temperature
1.4
10
1
1
IS (A)
T j =150 o C
T j =25 o C
VGS(th)(V)
0.6 0.2 -50
0.1
0.01 0 0.4 0.8 1.2 1.6
0
50
100
150
V SD , Source-to-Drain Voltage (V)
T j , Junction Temperature ( o C )
Fig 5. Forward Characteristic of
Reverse Diode
11/16/2007 Rev.1.00
Fig 6. Gate Threshold Voltage v.s. Junction Temperature
3
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SSM2602GY
f=1.0MHz
14 1000
12
VGS , Gate to Source Voltage (V)
I D =5.3A V DS =16V
C iss
10
C (pF)
8
C oss
100
6
C rss
4
2
0 0 5 10 15 20 25
10
1
5
9
13
17
21
25
29
Q G , Total Gate Charge (nC)
V DS , Drain-to-Source Voltage (V)
Fig 7. Gate Charge Characteristics
Fig 8. Typical Capacitance Characteristics
100
1
Duty factor=0.5
Normalized Thermal Response (Rthja)
0.2
10
1ms ID (A)
1
0.1
0.1
0.05
10ms 100ms 1s DC
PDM
0.01
t T
Single Pulse
0.01 Duty factor = t/T Peak Tj = PDM x Rthja + T a Rthja = 156/W
0.1
T A =25 o C Single Pulse
0.01 0.1 1 10
0.001
100 0.0001 0.001 0.01 0.1 1 10 100 1000
V DS , Drain-to-Source Voltage (V)
t , Pulse Width (s)
Fig 9. Maximum Safe Operating Area
Fig 10. Effective Transient Thermal Impedance
VDS 90%
VG QG 4.5V QGS QGD
10% VGS td(on) tr td(off) tf Charge Q
Fig 11. Switching Time Waveform
11/16/2007 Rev.1.00
Fig 12. Gate Charge Waveform
4
www.SiliconStandard.com
SSM2602GY
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties.
11/16/2007 Rev.1.00
www.SiliconStandard.com
5


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